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-- Company: 
-- Engineer:
--
-- Create Date:   17:00:36 04/23/2012
-- Design Name:   
-- Module Name:   C:/Users/ulab/Desktop/compe-bricks/hardware/compe-bricks/adc_test.vhd
-- Project Name:  compe-bricks
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ADC_accell
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY adc_test IS
END adc_test;
 
ARCHITECTURE behavior OF adc_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ADC_accell
    PORT(
         clk_in : IN  std_logic;
         eoc : IN  std_logic;
         clk_out : INOUT  std_logic;
         oe : OUT  std_logic;
         start : OUT  std_logic;
         addrA : INOUT  std_logic;
         ale : OUT  std_logic;
			data_ready : out std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_in : std_logic := '0';
   signal eoc : std_logic := '0';
   signal clk_out : std_logic;
   signal addrA : std_logic;

 	--Outputs
   signal oe : std_logic;
   signal start : std_logic;
   signal ale : std_logic;
	signal data_ready : std_logic;

   -- Clock period definitions
   constant clk_in_period : time := 2 ms;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ADC_accell PORT MAP (
          clk_in => clk_in,
          eoc => eoc,
          clk_out => clk_out,
          oe => oe,
          start => start,
          addrA => addrA,
          ale => ale,
			 data_ready => data_ready
        );

   -- Clock process definitions
   clk_in_process :process
   begin
		clk_in <= '0';
		wait for clk_in_period/2;
		clk_in <= '1';
		wait for clk_in_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
			eoc <= '1';
			wait for 15 ms;
			eoc <= '0';
			wait for 15 ms;
			eoc <= '1';
			wait for 15 ms;
			eoc <= '0';
			wait for 15 ms;
			eoc <= '1';

      -- insert stimulus here 

      wait;
   end process;

END;
